1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for testing stuck-at faults and delay faults of a repair circuit, for example, in a memory having a redundant configuration and relates to a design support software system and an automatic test pattern generation system.
2. Background Art
Some techniques for detecting faults of devices in a manufacturing test use a BIST (built-in self test) circuit, for example, which tests a memory circuit set in a semiconductor integrated circuit.
Methods for detecting faults in a memory circuit include, for example, a comparator-type BIST method in which comparison is made between written-in data and read-out data for determination on the presence of faults, or a compressor-type BIST method in which read-out data is compressed in a BIST circuit and a determination on the presence of faults is made based on the compressed data.
Further, some memory circuits have a memory having a redundant configuration for repairing a faulty cell. This memory having a redundant configuration has a redundant cell for repair other than normal memory cells, and where fault occurs in a memory cell, offers repair by avoiding the faulty cell and using the redundant cell, so that a normal operation as a memory circuit is carried out.
The memory having a redundant configuration includes, for example, normal memory cells, a redundant cell, and a repair logic consisting of a blowing type fuse circuit, a fuse register, a repair code decoding circuit, and an input-output switching circuit. It should be appreciated that a technology for distributing the repair logic as a logic circuit outside a memory circuit is referred to as a “soft-macro type redundancy repair technology”.
When the above fuse circuit is used for repair, a repair code is determined based on the results of a test for the memory circuit. Then, according to the repair code, a corresponding fuse bit in the fuse circuit is fused so as to be fixed in a repaired state. Then, switching is carried out by the input-output switching circuit from the faulty cell of the normal memory cells to the redundant cell, so that normal reading-out/writing-in operation avoiding the faulty cell can be performed (see Japanese Laid-Open Publication No. 2004-192712, for example).
When the memory having a redundant configuration is tested by means of a BIST circuit, the comparator-type BIST method is typically used. In this case, a repair code is produced by a BIRA (built-in redundancy allocation) circuit based on the comparison results produced through the comparator-type BIST method.
Under such circumstances, where the soft-macro type redundancy repair technology mentioned above is used, detection of stuck-at faults, or static faults, of a semiconductor integrated circuit embedded in the memory circuit is performed by providing a bypass circuit for bypassing the memory circuit, giving a scan design to the fuse register, and automatically generating a stuck-at fault test pattern.
By “scan design” is meant to constitute a shift register by replacing a register in a logic circuit with a scan register having a test input and a test output, and connecting the test input and the test output in series with each other. Thus, signal setting and observation can be directly performed for the register from an external terminal.
In this way, stuck-at faults of the decoding circuit and the input-output switching circuit are tested by giving a scan design to the fuse register, and adding a bypass circuit for bypassing the memory circuit. Once the bypass circuit is added after giving a scan design to the fuse register, stuck-at faults of the decoding circuit and the input-output switching circuit become testable.
On the other hand, detection of delay faults that cause delay in the semiconductor integrated circuit is performed by automatically generating a sequential delay fault test pattern, in a state where reading/writing for the memory circuit is possible.
In case the sequential delay fault test pattern for performing reading/writing for the memory cells is automatically generated in order to detect delay faults, the input-output switching circuit is required to be controlled by inputting a repair code into the fuse register, so as not to produce a test pattern for performing reading/writing for the faulty cell.
In this regard, in case a scan design has been provided to the fuse register in order to test stuck-at faults, as described above, the delay fault test pattern has to be configured as a pattern for inputting/outputting a repair code into/from the fuse register.
Accordingly, while the fact that the test pattern is for detecting delay faults remains unchanged, a different test pattern for every repair code has to be set by a tester. In other words, a measure, such as to provide a pattern storage capacity to the tester for inputting the test pattern is necessitated, which storage capacity has to be sufficient for holding shift patterns corresponding to all the repair codes, thus raising a problem of increasing cost.